The present invention relates, in general, to logic gates and, more particularly, to differential logic gates with improved output logic drive.
Differential logic gates have a wide range of applications. Clock generation circuits, for example, provide an excellent application for which differential logic gates can be used. Clock generation circuits implemented with differential logic gates have the capability of significantly reducing the clock skew and jitter over an equivalent design implemented with single-ended logic families. In fact, applications requiring superior noise immunity are especially suited for differential logic implementations. Differential inputs used in differential logic families promote common mode rejection of cross talk noise and EMI radiation.
Semiconductor process improvements tend to shrink the geometric dimensions of semiconductor devices. Speed and power consumption are two examples of motivations for performance enhancements. As newer generations of superior semiconductor devices are manufactured, it is advantageous to replace older logic families with the newer logic generations, which do not dissipate as much energy as the older logic families and yet demonstrate superior speed performance. One problem, however, induced by transplanting the newer logic families into applications utilizing older logic families, is the reduction in current conduction capability of the newer logic families due to increased current densities. As the current density increases, the base-emitter voltage, Vbe, of the newer devices also increase, creating a larger voltage drop across emitter follower output drivers.
Referring to FIG. 1, an enhanced output drive, differential logic circuit 10 is illustrated. Transistor 24 is an emitter follower output driver receiving base current drive from p-type, Metal Oxide Semiconductor (PMOS) device 16. Transistors 18 and 20 form the typical differential logic input, which receive complimentary input logic levels. A logic high voltage at the IN terminal causes transistor 18 to transition to an on, or non-conductive, state which brings the gate terminal of inverting PMOS transistor 16 to a logic low potential. Transistor 16 begins to conduct current, since the base terminal of transistor 24 is substantially equal to Vcc. Transistor 16 supplies base current drive to the base terminal of transistor 24 only when transistor 20 is in a non-conductive state. In the absence of PMOS transistor 16, the required base current drive would be derived from resistor 14 operating from top rail supply potential Vcc. The resulting output logic high voltage, VOH, would be VOH=VCCxe2x88x92V14xe2x88x92Vbe-24, where V14 is the voltage drop across resistor 14 and Vbe-24 is the base-emitter voltage drop across transistor 24. As the logic at terminal IN inverts to a logic low, PMOS transistor 16 turns off, or transitions to a non-conductive state, thereby canceling base current drive into transistor 24. An inherent speed problem exists with differential logic circuit 10, such that PMOS transistor 16 switches on and off depending on the logic state at terminal IN. PMOS transistor switches on during a VOH output condition and switches off during a low output voltage VOL condition. Differential logic circuit 10 also introduces the need to mix MOS technology with bipolar technology, which complicates the semiconductor process and drives the manufacturing costs upward.
A need exists, therefore, for a differential logic gate, which provides improved output logic drive, at faster speeds with reduced manufacturing complexity.